1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly to a method of using surface treatment to form doped region in the hard mask atop gate structure and in the interlayer dielectric layer.
2. Description of the Prior Art
In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrodes of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers.
However, in current fabrication of high-k metal transistor, particularly during the stage for forming self-aligned contacts (SAC), hard mask atop metal gate is often removed excessively thereby causing contact plugs to contact metal gates directly and resulting in short circuits. Hence, how to resolve this issue has become an important task in this field.